Zentel DDR1 SDRAM

Zentel DDR1 SDRAM is a 4-bank x 8,388,608-word x 8bit, or 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on data strobe, and output data. Data strobe are referenced on both edges of CLK. The devices achieve a very high-speed clock rate up to 200MHz.

Features

V_DD=V_DDQ=2.5V+0.2V
Double data rate architecture; two data transfers per clock cycle
Bidirectional, data strobe (DQS) is transmitted/received with data
Differential clock input (CLK and /CLK)
DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
Commands entered on each positive CLK edge
Data and data mask referenced to both edges of DQS
4 bank operation controlled by BA0, BA1 (Bank Address)
CAS latency – 2/2.5/3 (programmable)

Burst length – 2/4/8 (programmable)
Burst type – Sequential / Interleave (programmable)
Auto Precharge / All Bank Precharge controlled by A10
Support concurrent Auto Precharge
8192 refresh cycles / 64ms (4 banks concurrent refresh)
Auto Refresh and Self Refresh
Row address A0-12/Column address A0-9(x8) /A0-8(x16)
SSTL_2 Interface
Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch

Zentel DDR1 SDRAM

Features

Block Diagram

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