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Texas Instruments TDA4VE-Q1/TDA4AL-Q1/TDA4VL-Q1 SoC Processors

Texas Instruments TDA4VE-Q1/TDA4AL-Q1/TDA4VL-Q1 SoC Processors are based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications. These devices are built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The Texas Instruments TDA4AL-Q1 provides high-performance computing for both traditional and deep learning algorithms at industry-leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next-generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, current Arm and GPU processors for general computing, an integrated next-generation imaging subsystem (ISP), video codec, and isolated MCU island. All are protected by automotive-grade safety and security hardware accelerators.

Features

Processor cores
- Two C7x floating point, vector DSP, up to 1.0GHz, 160 GFLOPS, 512 GOPS
- Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0GHz
- Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2GHz
  - 1MB shared L2 cache per dual-core Cortex-A72 cluster
  - 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
- Up to six Arm Cortex-R5F MCUs at up to 1.0GHz
  - 16K I-Cache, 16K D-Cache, 64K L2 TCM
  - Two Arm Cortex-R5F MCUs in isolated MCU subsystem
  - Four (TDA4VE) or Two (TDA4AL/TDA4VL) Arm Cortex-R5F MCUs in general compute partition
- GPU IMG BXS-64-4, 256kB Cache, up to 800MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and TDA4VL)
- Custom-designed interconnect fabric supporting near-max processing entitlement
Memory subsystem
- Up to 4MB of on-chip L3 RAM with ECC and coherency
  - ECC error protection
  - Shared coherent cache
  - Supports internal DMA engine
- Up to Two External Memory Interface (EMIF) modules with ECC
  - Supports LPDDR4 memory types
  - Supports speeds up to 4266 MT/s
  - Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17GB/s per EMIF
- General-Purpose Memory Controller (GPMC)
- One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in the MAIN Domain, protected by ECC
Functional Safety
- Functional Safety-Compliant targeted (on select part numbers)
- Developed for functional safety applications
- Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
- Systematic capability up to ASIL-D/SIL-3 targeted
- Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
- Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
- Hardware integrity up to ASIL-D/SIL-3 targeted for the Extended MCU (EMCU) portion of the Main Domain
- Safety-related certification
  - ISO 26262 planned

Device security (on select part numbers)
- Secure boot with secure runtime support
- Customer programmable root key, up to RSA-4K or ECC-512
- Embedded hardware security module
- Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES, and 3DES
High-speed serial interfaces
- One PCI-Express® (PCIe) Gen3 controllers
  - Up to four lanes per controller
  - Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
- One USB 3.0 dual-role device (DRD) subsystem
  - Enhanced SuperSpeed Gen1 Port
  - Supports Type-C switching
  - Independently configurable as a USB host, USB peripheral, or USB DRD
- Two CSI2.0 4L RX plus Two CSI2.04L TX
Automotive interfaces
- Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support
Display subsystem
- One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)
- One eDP 4L (TDA4VE/TDA4VL)
- One DPI
Audio interfaces
- Five Multichannel Audio Serial Port (MCASP) modules
Video acceleration
- TDA4VE: H.264/H.265 Encode/Decode (up to 480MP/s)
- TDA4AL: H.264/H.265 Encode only (up to 480MP/s)
- TDA4VL: H.264/H.265 Encode/Decode (up to 240MP/s)
Ethernet
- Two RMII/RGMII interfaces
Flash memory interfaces
- Embedded MultiMediaCard Interface ( eMMC™ 5.1)
- One Secure Digital 3.0/Secure Digital Input Output 3.0 interface (SD3.0/SDIO3.0)
- Two simultaneous flash interfaces configured as
  - One OSPI or HyperBus™ or QSPI, and
  - One QSPI
System-on-Chip (SoC) architecture
- 16nm FinFET technology
- 23mm x 23mm, 0.8mm pitch, 770-pin FCBGA (ALZ)
Companion Power Management ICs (PMIC)
- Functional Safety-Compliant support up to ASIL-D / SIL-3 targeted
- Flexible mapping to support different use cases

Applications

Advanced Driver Assistance System (ADAS)
Machine vision
Industrial transport

Parking assist
Retail automation
Surveillance

Resources

Linux®, QNX, or RTOS Software Development Kit (SDK) for TDA4x SoCs
C7000 Code Generation Tools – Compiler
Code Composer Studio™ Integrated Development Environment (IDE)
Safety Compiler Qualification Kit
System Configuration Tool

Evaluate Deep Learning Inference Performance on TDA4x Processors
Industrial Mobile Robots (AGV/AMR)
Motor Drives Resources
Sensor Resources

Texas Instruments TDA4VE-Q1/TDA4AL-Q1/TDA4VL-Q1 SoC Processors

Features

Applications

Resources

Videos

Functional Block Diagram

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