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http://www.ti.com/general/docs/suppproductinfo.tsp?distId=26&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Flmk1d2104″>View Datasheet
Texas Instruments LMK1D210x Low Additive Jitter LVDS Buffer distributes two clock inputs (IN0 and IN1) to a total of up to 8 pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to 4 LVDS outputs. The inputs can be LVDS, LVPECL, HCSL, CML, or LVCMOS. The LMK1D210x is specifically designed for driving 50Ω transmission lines. In the case of driving the inputs in single-ended mode, the appropriate bias voltage must be applied to the unused negative input pin.
Using the control pin (EN), output banks can either be enabled or disabled. If this pin is left open, two buffers with all outputs are enabled, if switched to a logic “0”, both banks with all outputs are disabled (static logic “0”), if switched to a logic “1”, one bank and its outputs are disabled while another bank with its outputs is enabled. The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The Texas Instruments LMK1D210x operates in a 1.8V, 2.5V, or 3.3V supply environment and is characterized from –40°C to 105°C (ambient temperature).
