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Texas Instruments LMK04714-Q1 Dual-Loop Clock Jitter Cleaner

Texas Instrument LMK04714-Q1 Dual-Loop Clock Jitter Cleaner is a high-performance clock conditioner with JEDEC JESD204B/C support for space applications. Each of the 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters. The Texas Instrument LMK04714-Q1 can also drive other logic devices using the device and SYSREF clocks. The SYSREF can be provided using both DC and AC coupling. Since this device is not limited to JESD204B/C applications, the 14 outputs can be configured individually as high-performance outputs for traditional clocking systems.

Features

AEC-Q100 Grade 1 (-40°C to 125°C)
3255MHz maximum clock output frequency
Multi-mode: dual PLL, single PLL, and clock distribution
6GHz external VCO or distribution input
Ultra-low noise, at 2500MHz
- 54fs RMS jitter (12kHz to 20MHz)
- 64fs RMS jitter (100Hz to 20MHz)
- -157.6dBc/Hz noise floor
Ultra-low noise at 3200MHz
- 61fs RMS jitter (12kHz to 20MHz)
- 67fs RMS jitter (100Hz to 100MHz)
- -156.5dBc/Hz noise floor
PLL2
- PLL FOM of -230dBc/Hz
- PLL 1/f of -128dBc/Hz
- Phase detector rate up to 320MHz
- Two integrated VCOs: 2440MHz to 2600MHz and 2945MHz to 3255MHz
Up to 14 differential device clocks
- CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs

Up to 1 buffered VCXO/XO output
- LVPECL, LVDS, 2xLVCMOS programmable
1-1023 CLKOUT integer divider
1-8191 SYSREF integer divider
25ps step analog delay for SYSREF clocks
Digital delay and dynamic digital delay for device clocks and SYSREF
Holdover mode with PLL1
0-delay with PLL1 or PLL2
High reliability
- Controlled baseline
- One assembly/test site
- One fabrication Site
- Extended product life cycle
- Extended product-change notification
- Product traceability

Applications

Automotive radar
Data converter clocking
LIDAR

Texas Instruments LMK04714-Q1 Dual-Loop Clock Jitter Cleaner

Features

Applications

Functional Block Diagram

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