SMARTsemi DDR3 Memory ICs

SMARTsemi DDR3 Memory ICs feature a double data rate architecture to achieve high-speed operation. The ICs achieve high-speed double-data-rate transfer rates of up to 1866Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3(L) DRAM key features, and all control and address inputs are synchronized with a pair of externally supplied differential clocks.

Features

Interface and Power Supply
- SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V)
- SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
JEDEC DDR3(L) Compliant
- 8n Prefetch Architecture
- Differential Clock (CK/CK) and Data Strobe
(DQS/DQS)
- Double-data rate on DQs, DQS, and DM
Data Integrity
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Partial Array Self Refresh (PASR)
- Power Down Mode
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240ohm ± 1%)

Signal Synchronization
- Write Leveling via MR settings
- Read Leveling via MPR
Programmable Functions
- CAS Latency (5/6/7/8/9/10/11/12/13/14)
- CAS Write Latency (5/6/7/8/9/10)
- Additive Latency (0/CL-1/CL-2)
- Write Recovery Time (5/6/7/8/10/12/14/16)
- Burst Type (Sequential/Interleaved)
- Burst Length (BL8/BC4/BC4 or 8 on the fly)
- Self Refresh Temperature Range (Normal/Extended)
- Output Driver Impedance (34/40)
- On-Die Termination of RTT_Nom (20/30/40/60/120)
- On-Die Termination of RTT_WR (60/120)
- Precharge Power Down (slow/fast)

SMARTsemi DDR3 Memory ICs

Features

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