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pSemi UltraCMOS® Power Limiter Evaluation Kits provide demonstration and development platforms for the UltraCMOS Power Limiters. The UltraCMOS Power Limiters provide a monolithic alternative to discrete, PIN-diode limiters based on gallium-arsenide (GaAs) technology and protect devices against excessive RF power, intentional jamming, and ESD events.
The UltraCMOS® Power Limiter Evaluation Kits each feature a pre-mounted target UltraCMOS Power Limiter IC, along with support components and four SMA connectors. The uni-directional RF input and output are connected to the RF1 and RF2 port through a 50Ω transmission line via SMA connectors J2 and J3. A through 50Ω transmission line is available via SMA connectors J5 and J6. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The 2-pin connector J4 is connected to the external bias VCTRL.
These Evaluation Kits provide an example application circuit, allowing rapid prototyping when incorporated into existing designs.
