Microchip Technology SAMA5D29 Automotive Arm® Cortex®-A5 CPU-Based MPUs

Microchip Technology SAMA5D29 Automotive Arm® Cortex®-A5 CPU-Based MPUs are high-performance, low-power embedded microprocessors running up to 500MHz. The AEC-Q100 Grade 2 qualified SAMA5D29 MPUs offer support for multiple memories such as DDR2, DDR3L, LPDDR2, LPDDR3, QSPI, and e.MMC Flash. These devices integrate powerful peripherals for connectivity and user interface applications, including two ISO-compliant CAN-FD interfaces.

Advanced security functions include Arm® TrustZone®, tamper detection, secure data storage, and secure boot. The devices also feature high-performance crypto accelerators (AES, SHA, and TRNG). The Microchip Technology SAMA5D29 Automotive MPUs are qualified for an extended, industrial -40°C to +105°C temperature range and are delivered with free Linux® distributions, MPLAB X IDE, MPLAB Harmony v3, and bare metal C examples.

Features

Arm Cortex-A5 core
- Armv7-A architecture
- Arm® TrustZone
- NEON™ media processing engine
- Up to 500MHz
- 8-Kbytes ETM/ETB
Memory architecture
- Memory Management Unit (MMU)
- 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
- 128-Kbyte L2 cache configurable to be used as an internal SRAM
- 1x 128-Kbyte scrambled internal SRAM
- 1x 160-Kbyte internal ROM
  - 64-Kbyte scrambled and maskable ROM embedding bootloader/secure bootloader
  - 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
- High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting up to 512Mbytes 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off only) / LPDDR1/LPDDR2/LPDDR3, including “on-the-fly” encryption/decryption path
- 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
System running up to 166MHz in typical conditions
- Reset Controller (RSTC), Shutdown Controller (SHDWC), Periodic Interval Timer (PIT), independent Watchdog Timer (WDT), and secure Real-Time Clock (RTC) with clock calibration
- 1x 600MHz to 1200MHz PLL for the system and one 480MHz PLL optimized for high-speed USB
- Digital fractional PLL for audio (11.2896MHz and 12.288MHz)
- Internal low-power 12MHz RC and 32kHz typical RC oscillator
- Selectable 32.768Hz low-power crystal oscillator and 8MHz to 24MHz crystal oscillator
- 51x DMA channels including 2x 16-channel 64-bit Central DMA controllers
- 1x Advanced Interrupt Controller (AIC)
- 1x Secure Advanced Interrupt Controller (SAIC)
- 3x programmable external clock signals
Low-power modes
- Ultra-low-power mode with fast wake-up capability
- Low-power Backup mode with 5-Kbyte SRAM and asynchronous partial wake-up features
  - Wake up from up to 9x wake-up pins, UART reception, analog comparison
  - Fast wake-up capability
  - Extended Backup mode with DDR in Self-Refresh mode
Peripherals
- LCD TFT controller (LCDC) up to 1024×768 or 1280×768 (still image). 4x overlays, rotation, postprocessing, and alpha blending, 24-bit parallel RGB interface
- ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5Mpixel sensors with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome, and JPEG-compressed sensor interface
- 2x Synchronous Serial Controllers (SSC), 2x Inter-IC Sound Controllers (I2SC), and 1x Stereo Class D amplifier (CLASSD)
- 1x Peripheral Touch Controller (PTC) with up to 8x X-lines and 8x Y-lines (64-channel capacitive touch)
- 1x Pulse Density Modulation Interface Controller (PDMIC)
- 1x USB device high-speed port (UDPHS) and 1x USB host high-speed port or 2x USB host high-speed ports (UHPHS)
- 1x USB host high-speed port with a High-Speed Inter-Chip (HSIC) interface
- 1x 10/100 Ethernet MAC (GMAC)
  - Energy efficiency support (IEEE® 802.3az standard)
  - Ethernet AVB support with IEEE802.1AS timestamping
  - IEEE802.1Qav credit-based traffic-shaping hardware support
  - IEEE1588 Precision Time Protocol (PTP)
- 2x high-speed memory card hosts
  - SDMMC0: SD 3.0, eMMC 4.51, 8 bits
  - SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
- 2x host/client Serial Peripheral Interfaces (SPI)
- 2x Quad Serial Peripheral Interfaces (QSPI)
- 5x FLEXCOMs (USART, SPI, and TWI)
- 5x UARTs
- 2x host CAN-FD (MCAN) controllers with SRAM-based mailboxes, time- and event-triggered transmission, and a 32-bit Time Stamping Unit (TSU)
- 1x Rx-only UART in the backup area (RXLP)
- 1x Analog Comparator Controller (ACC) in the backup area
- 2x 2-wire interfaces (TWIHS) up to 400-Kbits/s supporting the I²C protocol and SMBUS
- 1x full-featured 4-channel, 16-bit Pulse Width Modulation (PWM) controller
- 2x 3-channel, 32-bit Timer/Counters (TC), supporting basic PWM modes
- 1x 12-channel, 12-bit Analog-to-Digital Converter (ADC) with resistive touchscreen capability

Safety
- Zero-power Power-on Reset (POR) cells
- Main crystal clock failure detector
- Write-protected registers
- Integrity Check Monitor (ICM) based on SHA256
- Memory Management Unit (MMU)
- Independent watchdog
Security
- 5-Kbytes of internal scrambled SRAM
  - 1-Kbyte non-erasable on tamper detection
  - 4-Kbytes erasable on tamper detection
- 256-bits of scrambled and erasable registers
- Up to 8x tamper pins for static or dynamic intrusion detections
- Secure bootloader
- On-the-fly AES encryption/decryption on DDR and QSPI memories (AESB)
- RTC including timestamping on security intrusions
- Programmable fuse box with 544x fuse bits (including JTAG protection and BMS)
Hardware cryptography
- SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2
- AES: 256-, 192-, 128-bit key algorithms, compliant with FIPS PUB 197
- TDES: 2-key or 3-key algorithms, compliant with FIPS PUB 46-3
- True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs 140-2 and 140-3
Up to 128x I/Os
- Fully programmable through set/clear registers
- Multiplexing of up to 8x peripheral functions per I/O line
- Each I/O line can be assigned to a peripheral or used as a general-purpose I/O
- The PIO controller features a synchronous output providing up to 32-bits of data output in one write operation
Available in a 289-ball LFBGA, 14mm², 0.8mm pitch package

Specifications

32-bit data bus width
500MHz maximum clock frequency
1.1V to 1.32V operation range

32MB L1 cache instruction memory
32MB L1 cache data memory
-40°C to +105°c opoerting temperature range

Application Schematics

Microchip Technology SAMA5D29 Automotive Arm® Cortex®-A5 CPU-Based MPUs

Microchip Technology SAMA5D29 Automotive Arm® Cortex®-A5 CPU-Based MPUs

Features

Specifications

Application Schematics

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