Microchip Technology PIC18F24/25Q24 Microcontrollers

Microchip Technology PIC18F24/25Q24 Microcontrollers are part of the PIC18-Q24 microcontroller family of 28/40/44/48-pin devices for sensor-interfacing, real-time control, and communication applications. The PIC18F24Q24 offers 16KB of memory, 1KB of Data SRAM, and 512B of EEPROM. Meanwhile, the PIC18F25Q24 provides 32KB of memory, 2KB of Data SRAM, and 512B of EEPROM. The devices have 24x I/O pins, including four MVIO pins powered by V_DDIO².

The Microchip PIC18F24/25Q24 Microcontrollers also feature a vectored interrupt controller with fixed latency for handling interrupts, system bus arbiter, Direct Memory Access (DMA) capabilities, Universal Asynchronous Receiver-Transmitter (UART) with support for asynchronous, DMX-512, Digital Addressable Lighting Interface (DALI®) and Local Interconnect Network (LIN) protocols; Serial Peripheral Interface (SPI), and I²C. Furthermore, the family includes memory features such as Memory Access Partition (MAP) and the Device Information Area (DIA), which stores factory calibration values to help improve temperature sensor accuracy.

Features

Multi-Voltage I/O (MVIO):
- MVIO-powered pins support operation from 1.62V to 5.5V
- This domain is independent of the main V_DD voltage level
- Voltage monitoring on the additional voltage domain with programmable trip points
Programming and Debugging Interface Disable (PDID), the ICSP interface can be disabled to prevent external memory access or modifications
Vectored Interrupt (VI) capability – faster interrupt response time
- Selectable high/low priority
- Programmable vector table base address
- Fixed interrupt latency of 3x instruction cycles
- Backward compatible with previous interrupt capabilities
Memory Access Partition (MAP), the program Flash memory can be partitioned into:
- Application block
- Boot block
- Storage Area Flash (SAF) block with SAFLOCK to prevent modifications
Programming/Debugging:
- Programming and Debugging Interface Disable (PDID)
- In-Circuit Serial Programming™ (ICSP™) via 2x pins
- In-Circuit Debug (ICD) with 3x breakpoints via 2x pins
- Debug integrated on-chip
4x Direct Memory Access (DMA) controller Analog-to-Digital Converter with Computation (ADCC):
- 10-bit ADC with computation up to 300ksps
- Up to 30x external channels
- Automated math functions on input signals such as averaging, filter calculations, oversampling, and threshold comparison
- Operates in Sleep
- 5x internal analog channels
- Hardware Capacitive Voltage Divider (CVD) support: automates touch sampling and reduces software size / CPU usage
8-Bit Digital-to-Analog Converter (DAC):
- Buffered output available on 2x I/O pins
- Internal connections to ADC and Comparators
2x High-Speed Comparators (CMP):
- Configurable power vs speed modes
- Configurable output polarity
- External output via Peripheral Pin Select
2x Zero-Cross Detect (ZCD), detect when the AC signal on the pin crosses ground
3x 16-bit dual PWMs provide 6x PWM outputs

Voltage reference:
- Fixed voltage reference with 1.024V, 2.048V, and 4.096V output levels
- Internal connections to ADC, Comparator, and DAC
UART with hardware support for LIN/DMX
- DMA compatible
- Asynchronous UART, RS-232, RS-485 compatible
- Programmable 1, 1.5, and 2 stop bits
2x SPI modules:
- Configurable length bytes
- Arbitrary length data packets
- Transmit-without-Receive and Receive-without-transmit option
- Transfer byte counter
- Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities
2x I²C module, SMBus and PMBus™ compatible:
- 7-bit and 10-bit addressing modes with address masking modes
- Dedicated address, transmit / receive buffers, and DMA capabilities
- I²C, SMBus 2.0/3.0, and 1.8V input level selections
- Multi-Master mode, including self-addressing
Device Information Area (DIA) stores:
- Temperature Indicator factory calibrated data
- Fixed Voltage Reference measurement data
- Microchip Unique Identifier
Low power mode:
- Sleep: < 1μA typical at 3V and lowest power consumption
- Doze: CPU and Peripherals running at different cycle rates (typically, CPU is lower)
- Idle: CPU Halted while peripherals operate
Peripheral Module Disable (PMD), selectively disable the hardware module to minimize active power consumption of unused peripherals
Device I/O port features:
- 24x I/O pins including 4x MVIO pins powered by V_DDIO² (PIC18F24/25/26Q24)
- 35x I/O pins including 12x MVIO pins powered by V_DDIO² (PIC18F45/46Q24)
- 43x I/O pins including 12x MVIO pins powered by V_DDIO² (PIC18F55/56Q24)
- MVIO pins support a voltage range of 1.62V through 5.5V
- Individually programmable I/O direction, open-drain, slew rate, and weak pull-up control
- Low-voltage interface on all I/O pins using LV-TTL input buffer
- Interrupt-on-change on most pins
- 3x programmable external interrupt pins

Applications

Sensor-interfacing
Real-time control
Communication

Microchip Technology PIC18F24/25Q24 Microcontrollers

Features

Applications

Block Diagram

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