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Design Gateway SATA3 Host CPUless IP Core is designed to be an all-in-one system that contains the application layer, transport layer, and link layer in one IP. This helps the connection with the PHY layer implemented by the transceiver without CPU and DDR usage. The SATA Physical layer is designed by HDL code for controlling transceiver following SATA protocol and is the interface module connected between SATA3H-CL IP and SATA device. This SATA3 IP core PHY is provided in the reference design in the release stuff for the IP customer. The SATA3 host IP core features dgIF typeS user interface that is very easy to access and comes with control and data interface.
The control interface includes general input parameters for Write and Read commands such as start address and transfer length. The data interface for Write command (Tx FIFO) and Read command (Rx FIFO) is designed by using the general FIFO interface. SATA3 IP core supports four ATA commands. The IDENTIFY DEVICE command checks SATA device capacity. SECURITY ERASE UNIT erases data in SATA device. WRITE DMA (EXT) to record data to SATA device and READ DMA (EXT) to read data back from SATA device.
