BittWare 520N-MX FPGA Accelerator Card

BittWare 520N-MX FPGA Accelerator Card features Intel’s® Stratix 10 MX2100 FPGA with integrated HBM2 memory. The 520N-MX FPGA Accelerator Card offers an HBM2 with 16GB at up to 512GB/s, allowing for the acceleration of memory-bound applications.

The BittWare 520N-MX board 100G QSFP28s are ideal for clustering, and OCuLink connectors allow expansion. The device supports both traditional HDL and higher abstraction C, C++, and OpenCL-based tool flows. The 520N-MX features a Board Management Controller (BMC) for advanced system monitoring and control, which streamlines platform integration and management.

Features

Intel Stratix 10 MX2100
16GB HBM2 up to 512GB/s
BittWare-optimized OpenCL BSP
Intel FPGA openCL software development kit (SDK)
- OpenCL support for software-orientated customers
- Abstraction for faster development
- Push-button flow for FPGA executable, driver, and API
- Add optimized HDL IP cores to OpenCL designs as libraries

Hardware description language (HDL)
- Traditional VHDL/Verilog support for hardware-orientated customers
- Hand-code for ultimate performance
- High-Level Synthesis (HLS) available for rapid development
- FPGA card designed to support standard Intel IP cores for Stratix 10

Specifications

FPGA
- Intel Stratix 10 MX
  - MX2100 in an F2597 package
  - 16GBytes on-chip High Bandwidth Memory (HBM2) DRAM, 410 GB/s (speed grade 2)
  - Core speed grade -2: I/O speed grade -2
On-board Flash
- 2Gbit Flash memory for booting FPGA
External memory
- 2x 288-pin DIMM slots each fitted with 16GB modules by default, i.e., 32GB total on board (options up to 256GB total)
Host interface
- x16 Gen3 interface direct to FPGA, connected to PCIe hard IP
QSFP cages
- 4 QSFP28 cages on front panel connected directly to FPGA via 16 transceivers
- User programmable low jitter clocking supporting 10/25/40/100GbE
- Each QSFP28 can be independently clocked
- Jitter cleaner for network recovered clocking
- 2 QSFP28s have available 100GbE MAC hard IP
OCuLink
- 2x edge connectors (A, B) @ 12.5G per lane (default); each supports PCIe Gen 3 x8 hard IP, GPIO, and PCIe master and optional input clocking
- 2x inner connectors (C, D) @ 25G per lane (optional); 1x 100GbE MAC hard IP per OCuLink
Board Management Controller
- Voltage, current, temperature monitoring
- Power sequencing and reset
- Field upgrades
- FPGA configuration and control
- Clock configuration
- Low bandwidth BMC-FPGA comms with SPI link
- USB 2.0
- PLDM support
- Voltage overrides

Cooling
- Double-width active heatsink (with fan) – standard
- Double-width passive heatsink – optional
- Double-width liquid cooling – optional
Electrical
- On-board power derived from 12V PCIe slot & two AUX connectors (one 8-pin, one 6-pin)
- Power dissipation is application-dependent
- Typical max power consumption 225W
Environmental
- +5°C to +35°C operating temperature
Quality
- Manufactured to ISO9001:2015 IPC-A-610-Class III
- RoHS compliant
- CE, FCC, and ICES approvals
Form factor
- Standard-height PCIe dual-slot board
- 4.376″ x 10.5″ (111mm x 266.7mm)
Development Tools
- FPGA development BIST – Built-In Self-Test for CentOS 7 provided with source code (pinout, gateware, PCIe driver & host test application)
- Application development Supported design flows – Intel FPGA OpenCL SDK, Intel High-Level Synthesis (C/C++) & Quartus Prime Pro (HDL, Verilog, VHDL, etc.)

Kit Contents

520N-MX FPGA board
USB cable (front panel access)
Built-In Self-Test (BIST)

OpenCL HPC Board Support Package (BSP)
1-year access to online developer site
1-year hardware warranty

BittWare 520N-MX FPGA Accelerator Card

Features

Specifications

Kit Contents

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