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Texas Instruments LMK5B33216 Network Synchronizer and Jitter Cleaner are designed to meet the stringent requirements of ethernet-based networking applications with < 5ns timing accuracy (class D). The network synchronizer integrates three DPLLs to provide hitless switching. It also has jitter attenuation, programmable loop bandwidth, and no external loop filters. This feature maximizes flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input. The APLL3 features an ultra-high-performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. It can generate 312.5MHz output clocks with 42fs typical/60fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. The APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain.
Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero delay and a phased buildout may be enabled to control the phase relationship from input to output. The device is fully programmable through an I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The Texas Instruments LMK5B33216 also features factory default ROM profiles as fallback options.









