Diodes Incorporated PI7C9X3G1224GP PCIe® 3.0 Packet Switch

Diodes Incorporated PI7C9X3G1224GP PCIe® 3.0 Packet Switch is a high-performance 12-port, 24-lane device ideal for edge computing, data storage, and communications infrastructure. The PI7C9X3G1224GP can also be incorporated into host bus adaptors (HBAs), industrial controllers, and network routers. The switch offers a low packet forwarding latency of <150ns (typical) and supports 24 lanes of Gen3 serializer / deserializer (SerDes) in flexible 3- to 12-port configurations. The architecture enables flexible port configurations by allocating variable lane widths for each port. For fan-out usages, a port can be configured as upstream and connected to multiple downstream ports. Diodes Incorporated PI7C9X3G1224GP PCIe 3.0 Packet Switch comes in a 324-pin flip-chip BGA package format.

Features

Integrated PCIe 3.0 clock buffer provides flexibility in design and overall cost reduction
Low packet forwarding latency for high-performance for data transmission
Supports multi-host application

High reliability – advanced error reporting, error handling mechanism, end-to-end data protection, hot-plug, and surprise removal
Diagnostic software tools help with debugging and project development

Applications

AI / deep learning
NAS / storage
Data center servers
Embedded systems
HBA / combo cards

Fail-over systems
Surveillance / security
Networking / switches
5G / wired communication
Printers / peripherals

Specifications

Port and lane configurations for 12-port/24-lane PCI Express Gen3 packet switch
- Configurable upstream port number up to 2
- Configurable upstream lane widths of x1, x2, x4, or x8
- Configurable downstream port number up to 11
- Configurable downstream lane widths of x1, x2, x4, or x8
Reference clock management
- Integrated PCIe Gen3 clock buffer for all downstream ports
- Supports 3 reference clock structures (common, SRNS, and SRIS)
- Handles SSC isolation up to 3 ports
- Provides 2 clock application modes (base and CDSR)
Power management
- Supports 7 power states (P0 / P0s / P1 / P1.1 / P1.2 / P2 / P1.2PG)
- Start-up power management scheme – “empty” hot-plug ports put in P2 state
- Continuous power management scheme – supports ASPM L1 sub-state (P1.1 / P1.2)
PHY and MAC layers
- PHY initial settings optionally programmable through JTAG, EEPROM, and SMBus/I²C
- Adaptive continuous time linear equalizer and 5-tap decision feedback equalizer for RX
- Adaptive and programmable 3-tap TX equalization
- RX polarity inversion and lane reversal
Data link layer
- Programmable ACK latency timer to respond ACK based on traffic condition
- Configurable flow control credit to balance bandwidth utilization and buffer usage
Transaction layer
- Packet forwarding options, including cut-through and store and forward
- Supports up to 512-byte maximum payload size
- Low packet forwarding latency <150ns (typical case)
- Access control service (ACS) for peer-to-peer traffic
- Address translation (AT) packet for SR-IOV application
- Supports atomic operation
- Supports multicast
- Provides performance visibility for ingress/egress packet types and packet counts

Multi-host application
- Supports up to 3 cross-domain end-point (CDEP) ports for host-to-host communications
- Supports fail-over using CDEP port
- Provides up to 8 physical or 16 virtual DMA channels, enabling communications among hosts and EPs
- Switch bifurcated up to 2 individual packet switches to allow 2 hosts operating independently
Reliability, availability, and serviceability
- Enhanced advanced error reporting
- End-to-end data protection with ECC
- Error handling mechanism
- Supports surprise hot removal
- Supports downstream port containment (DPC)
- Supports hot plug for upstream and downstream port
- Provides serial and parallel hot plug types
- Supports LED management
- Thermal sensor reporting operational temperature instantly
- IEEE 1149.1 and 1149.6 JTAG interface support
Advanced diagnostic tools
- PHY Eye™
- MAC Viewer™ (including embedded LA)
- PCIBUDDY™
- On-the-fly PRBS loopback test
- On-the-fly compliance pattern test
Side-band management interface
- I²C/SMBUS/JTAG
- SPI EEPROM
Standard compliance
- PCI Express base specification Revision 3.1
- PCI Express CEM specification Revision 3.0
- Advanced configuration power interface (ACPI) specification
- System management (SM) bus, Version 2.0
Power and package
- 0.95V and 1.8V power rails
- 5.33W power consumption
- Lead free and RoHS compliant
- Halogen- and antimony-free green device
- 324-pin flip-chip BGA package format
- 19mm x 19mm dimensions
-40°C to +85°C ambient operating temperature range

Diodes Incorporated PI7C9X3G1224GP PCIe® 3.0 Packet Switch

Features

Applications

Specifications

husseinkey ELECTRONICS®

COMPANY