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Texas Instruments AM64x Arm®-Based Single-Core Cortex®-A53 MCUs

Texas Instruments AM64x Arm®-Based Single-Core Cortex®-A53 MCUs are built for industrial applications. These applications include Programmable Logic Controllers (PLCs) and motor drives, which require a unique combination of communications and real-time processing with applications processing. The AM64x combines two instances of the Arm-Based device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm Cortex-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.

AM64x is architected to provide real-time performance through high-performance R5Fs, configurable SRAM partitioning, Tightly-Coupled Memory banks, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows AM64x to handle the tight control loops in servo drives. At the same time, the peripherals like FSI, GPMC, PWMs, sigma-delta decimation filters, and absolute encoder interfaces help enable several different architectures in these systems.

The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is supplied through TI’s Processor SDK Linux, which stays updated to the most current Long Term Support (LTS) Linux kernel, bootloader, and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.

The Texas Instruments AM64x provides flexible industrial communications capability, including full protocol stacks for EtherCAT SubDevice, EtherNet/IP adapter, PROFINET device, and IO-Link Master. The PRU-ICSSG further provides the ability for gigabit and TSN-based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC, including absolute encoder interfaces and sigma-delta decimation filters.

Functional safety features can be enabled through the integrated Cortex-M4F and dedicated peripherals, which can all be isolated from the rest of the SoC. The AM64x also supports a secure boot.

Features

Processor cores
- 1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHz
- Up to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processing
- 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
Industrial subsystem
- 2× gigabit Industrial Communication Subsystems (PRU_ICSSG)
  - Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more
  - Backward compatibility with 10/100Mb PRU_ICSS
  - Each PRU_ICSSG contains the following:
    - 2× Ethernet ports
    - 6 PRU RISC cores per PRU_ICSSG, with each core having:
    - Three Data RAMs with ECC
    - Eight banks of 30 × 32-bit register scratchpad memory
    - Interrupt controller and task manager
    - Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
    - 18× Sigma-Delta filters
    - 6× Multi-protocol position encoder interfaces
    - One Enhanced Capture Module (ECAP)
    - 16550-compatible UART with a dedicated 192MHz clock to support 12Mbps PROFIBUS
Memory subsystem
- Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
- DDR Subsystem (DDRSS)
- 1× General-Purpose Memory Controller (GPMC)
System on Chip (SoC) Services
- Device Management Security Controller (DMSC-L)
- Data Movement Subsystem (DMSS)
Security
- Secure boot supported
- Cryptographic acceleration supported
- Debugging security
- Trusted Execution Environment (TEE) supported
- Secure storage support
- On-the-Fly encryption support for OSPI interface in XIP mode
- Networking security support for data (Payload) encryption/authentication via packet-based hardware cryptographic engine
- Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
High-speed interfaces
- 1× Integrated Ethernet switch (CPSW3G) supporting
  - Up to 2 Ethernet ports
  - RMII (10/100)
  - RGMII (10/100/1000)
  - IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
  - Clause 45 MDIO PHY management
  - Energy-efficient Ethernet (802.3az)
- 1× PCI-Express Gen2 controller (PCI-E)
- 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)

General connectivity
- 6× Inter-Integrated Circuit (I²C) ports
- 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
- 1× Flash Subsystem (FSS) that can be configured as an Octal SPI (OSPI) Flash interface or one Quad SPI (QSPI)
- 1× 12-Bit Analog-to-Digital Converters (ADC)
- 7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
- 6× Fast Serial Interface Receiver (FSI_RX) cores
- 2× Fast Serial Interface Transmitter (FSI_TX) cores
- 3× General-Purpose I/O (GPIO) modules
Control interfaces
- 9x Enhanced Pulse-Width Modulator (EPWM) modules
- 3× Enhanced Capture (ECAP) modules
- 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
- 2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD support
Media and data storage
- 2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
Power management
- Simplified power sequence
- Integrated SDIO LDO for handling automatic voltage transition for SD interface
- Integrated voltage supervisor for safety monitoring of over-under voltage conditions
- Integrated power supply glitch detector for detecting fast supply transients
Functional Safety
- Functional Safety-Compliant targeted
  - The device developed for functional safety applications
  - Documentation will be available to aid IEC 61508 functional safety system design
  - Systematic capability up to SIL 3
  - Hardware integrity up to SIL 2 targeted
  - Safety-related certification
  - ECC or parity on calculation-critical memories
  - ECC and parity on select internal bus interconnect
  - Built-In Self-Test (BIST) for CPU and on-chip RAM
  - Error Signaling Module (ESM) with error pin
  - Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
  - Dedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features
    - Separate interconnect
    - Firewalls and timeout gaskets
    - Dedicated PLL
    - Dedicated I/O supply
    - Separate reset
SoC architecture
- Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces
- 16nm FinFET technology
- 17.2mm × 17.2mm, 0.8mm pitch, 441-pin BGA package

Applications

Programmable Logic Controller (PLC)
Motor drives
Remote I/O

Industrial robots
Condition-monitoring gateway

Texas Instruments AM64x Arm®-Based Single-Core Cortex®-A53 MCUs

Features

Applications

Functional Block Diagram

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