Infineon Technologies S70KL1282 & S70KL1283 Interface HyperRAMs

Infineon Technologies S70KL1282 and S70KL1283 Interface HyperRAMs are high-speed CMOS, self-refresh DRAMs with HYPERBUS™ interfaces. The DRAM array uses dynamic cells that require a periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. The memory is more accurately described as Pseudo-Static RAM (PSRAM).

Features

Interface
- HYPERBUS Interface
- 1.8V / 3.0V interface support
  - Single-ended clock (CK) – 11 bus signals
  - Optional differential clock (CK, CK#) – 12 bus signals
- Chip Select (CS#)
- 8-bit data bus (DQ[7:0])
- Hardware reset (RESET#)
- Bidirectional Read-Write Data Strobe (RWDS)
  - Output at the start of all transactions to indicate refresh latency
  - Output during reading transactions as Read Data Strobe
  - Input during write transactions as Write Data Mask
- Optional DDR Center-Aligned Read Strobe (DCARS)
  - During reading transactions, RWDS is offset by a second clock, phase-shifted from CK
- The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye
Performance, Power, and Packages
- - 200MHz maximum clock rate
  - DDR – transfers data on both edges of the clock
  - Data throughput up to 400MBps (3,200Mbps)
    - Configurable Burst Characteristics
      - Linear burst
      - Wrapped burst lengths
        
        16 bytes (eight clocks)
        
        32 bytes (16 clocks)
        
        64 bytes (32 clocks)
        
        128 bytes (64 clocks)
      - Hybrid option – one wrapped burst followed by linear burst on 64Mb. Linear Burst across die boundary is not supported.
    - Configurable output drive strength
    - Power Modes
      - Hybrid Sleep Mode
      - Deep Power Down
    - Array Refresh
      - Partial Memory Array (1/8, 1/4, 1/2, and so on)
      - Full
    - Package
      - 24-ball FBGA
    - - Industrial (I) –40°C to +85°C
      - Industrial Plus (V) –40°C to +105°C
      - Automotive, AEC-Q100 Grade 3 –40°C to +85°C Operating Temperature Range
      - Automotive, AEC-Q100 Grade 2 –40°C to +105°C

Infineon Technologies S70KL1282 & S70KL1283 Interface HyperRAMs

Features

Block Diagram

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