Zentel DDR2 SDRAM

Zentel DDR2 SDRAM features a double-data-rate architecture with two data transfers per clock cycle. The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture. A bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. DQS is edge-aligned with data for READs; center-aligned with data for WRITEs Differential clock inputs (CK and /CK). The DLL aligns DQ and DQS transitions with CK transitions.

Features

Double-data-rate architecture; two data transfers per clock cycle
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions

Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for better command and data bus efficiency
On-Die-Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe operation
Off-Chip Driver (OCD) impedance adjustment is not supported

Zentel DDR2 SDRAM

Features

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