Zentel DDR3 SDRAM

Zentel DDR3 SDRAM features a high-speed data transfer that is realized by the 8 bits prefetch pipelined architecture. The SDRAM has a double-data-rate architecture with two data transfers per clock cycle. They have a bi-directional differential data strobe (DQS and /DQS) and are transmitted/received with data for capturing data at the receiver. DQS is edge-aligned with data for READs; center-aligned with data for WRITEs. The differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions.

Features

The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
Double data-rate architecture: two data transfers per clock cycle
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Data mask (DM) for write data
Posted CAS by programmable additive latency for better command and data bus efficiency
On-Die Termination (ODT) for better signal quality
- Synchronous ODT
- Dynamic ODT
- Asynchronous ODT

Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Multi-Purpose Register (MPR) for pre-defined pattern readout
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
RESET pin for Power-up sequence and reset function
SRT(Self Refresh Temperature) range
- Normal/Extended
Auto Self-Refresh (ASR)
Programmable output driver impedance control
JEDEC compliant DDR3/DDR3L
Row-Hammer-Free (RH-Free): detection/blocking circuit inside

Zentel DDR3 SDRAM

Features

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