ISSI QuadRAM Devices

ISSI QuadRAM Devices contain 8Mb/16Mb/32Mb pseudo-static Random Access Memory (RAM) using a self-refresh DRAM array. These arrays are organized as 1M words by 8 bits, 2M words by 8 bits, and 4M words by 8 bits for 8Mb, 16Mb, and 32Mb, respectively. The QuadRAM devices support a Quad DDR interface that is compatible with JEDEC standard x4 xSPI flash. These devices support low signal count, hidden refresh operation, and automotive temperature operation. Due to DDR operation, the minimum transferred data size is a byte (8 bits) through 4 SIO pins.

Features

Industry-standard serial interface:
Quad DDR (x4 xSPI) interface:
- Command (1 byte) =SDR
- Address (2-byte) and Data = DDR
Low signal counts:
- 7 signal pins (CS#, SCLK, DQSM, and SIO0~SIO3)
High-performance:
- Double Data Rate (DDR) operation:
  - 200MHz (200MB/s) at 1.8V V_CC (1)
  - 133MHz (133MB/s) at 3V V_CC
- Source synchronous output signal during read operation (DQSM)
- Data mask during write operation (DQSM)
- Configurable latency for read/write operation
- Supports variable latency mode and fixed latency mode
- Configurable drive strength
- Supports wrapped burst mode and continuous mode
- Supports deep power-down mode
- Hidden refresh
Burst operation:
- Configurable wrapped burst length:
  - 16, 32, 64, and 128
- Continuous operation:
  - Continues read operation until the end of array address (no wrapped)
  - Continues write operation even after the end of array address (wrapped to first address)

Low power consumption:
- Single 1.7V to 1.95V voltage supply range
- Single 2.7V to 3.6V voltage supply range
Hardware features:
- SCLK serial clock input
- SIO0 – SIO3: serial data input or serial data output
- DQSM:
  - Output during command, address transactions as refresh collision indicator
  - Output during read data transactions as read data strobe
  - Input during write data transactions as write data mask
- RESET#: hardware Reset pin

ISSI QuadRAM Devices

Features

Block Diagram

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